1. Field of the Invention
The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (hereinafter referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.
2. Description of the Related Art
Currently, most MOSFETs used as a switch device have a planar type structure which takes up a lot of space to make a switch device of a memory array such as a 1T-DRAM etc. and there has been a limitation on a high integration of the memory array.
Also, most memory devices used as a memory cell have a planar type structure and have the above mentioned problem.
Particularly, since the high integration of a NAND flash memory array is easier than that of a NOR type, the NAND flash memory array is becoming popular as a mass non-volatile memory. But there has been a limitation on the high integration of the memory array by using a planar type memory cell.
To overcome the limitation of the planar type memory cell, various forms of memory devices having a vertical channel have being developed. However, so far, because the developed memory cells with a vertical channel are connected between bit lines of a single layer and word lines, it causes a problem that has a limitation on the high integration of a NAND flash memory array.
Furthermore, a conventional NAND flash memory array has a relatively weak effect on a channel of a memory cell. And it has a disturbance problem induced by an adjacent cell which shares a word line in an unselect bit line and a delay problem of an erasing speed due to the back tunneling.
To solve the problems of the conventional technology, an objective of the present invention is to provide a semiconductor device having a stacked array (STAR) structure which enables to widen a channel width of a vertical channel without limit and to form a single gate (SG), a double gate (DG) and a gate all around (GAA) as occasion demands.
In addition, another objective of the present invention is to provide a NAND flash memory array using the semiconductor device having a STAR structure as a memory cell, specifically, with the gate all around (GAA) structure by consisting of vertically stacked bit lines with memory cells connected in series and word lines wrapping around and sharing the several bit line layers, and to provide a fabrication method of the same.